1. Field of the Invention
This invention relates to semiconductor wafers and to manufacturing methods therefor, in which integrated circuits are formed on semiconductor wafers, which are cut into individual chips along scribing lines. This invention also relates to semiconductor devices having thin-film elements, which are formed on semiconductor wafers, and to manufacturing methods therefor.
This application claims priority on Japanese Patent Applications Nos. 2004-94621, 2004-94622 and 2005-75554, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Conventionally, semiconductor devices such as IC chips and LSI chips are manufactured using semiconductor wafers such as silicon wafers. In accordance with processes regarding thin film growth, photolithography, and etching, a plurality of integrated circuits (ICs) are formed on the same semiconductor wafer, which is subjected to cutting along scribing lines by use of dicing saws and the like so as to separate individual IC chips (or semiconductor chips), wherein semiconductor chip are each subjected to wire bonding with lead frames and are then subjected to resin molding.
Recently, a variety of electronic devices are manufactured and developed to realize highly-sophisticated functions, wherein they are reduced in sizes and dimensions realizing small thickness, whereby it is possible to produce composite semiconductor devices having multiple functions realizing functions of magnetic sensors, temperature sensors, and pressure sensors, which are put to practical uses. For example, composite semiconductor devices are accompanied with magnetic sensors, an example of which is disclosed in Japanese Patent Application Publication No. H05-121793, wherein IC chips are equipped with giant magnetoresistive effect elements (referred to as GMR elements).
FIG. 5 is a plan view showing a silicon wafer (or a semiconductor wafer) on which a plurality of semiconductor devices (i.e., semiconductor chips having magnetic sensors) are formed; FIG. 6 is an enlarged plan view showing a semiconductor device (i.e., a semiconductor chip having a magnetic sensor) and its periphery; and FIG. 7 is a cross-sectional view taken along line A-A in FIG. 6.
In FIG. 5, reference numeral 1 designates a silicon wafer in which scribing lines 3 are formed in a latticed manner on a silicon substrate (or a semiconductor substrate) so as to form a plurality of IC regions in a matrix manner, wherein the IC regions include IC components 4.
The IC components 4 each have a laminated structure in which wiring layers including electric circuits and insulating layers are alternately laminated together. Specifically, as shown in FIG. 6, the IC component 4 having a square shape includes an IC 5 implementing functions of various circuits such as an analog-to-digital converter (ADC), a memory (M), and an analog circuit (AnC), wherein GMR elements 6 to 9 are respectively arranged externally of and in proximity to prescribed sides (e.g., four sides in case of FIG. 6) of the IC 5 and are electrically connected with the IC 5. That is, a magnetic sensor is realized by the GMR elements 6 to 9.
Seal rings 11 are formed to encompass the IC component 4. Scribing lines 3, which are band-like regions having prescribed widths, are formed outside of the seal rings 11 in boundaries between adjacent IC regions. Channels 13 for separation of individual semiconductor chips are formed at the center of scribing lines 3.
FIG. 7 shows a cross-sectional structure with regard to the IC component 4, seal ring 11, and scribing line 3, wherein an integrated circuit (IC) implementing functions of an analog-to-digital converter (ADC), a memory (M), and an analog circuit (AnC) and an insulating layer 22 composed of silicon oxide are formed on a p-type silicon substrate (referred to as a p-Si substrate) 21; an insulating layer 23 is formed to cover the IC region and the insulating layer 22 such the one end thereof extends to the seal ring 11; a wiring layer 24a having a prescribed wiring pattern, an insulating layer 25a, a wiring layer 24b having a prescribed wiring pattern, and an insulating layer 25b are sequentially formed and laminated together on the insulating layer 23. The three insulating layers 23, 25a, and 25b are arranged at vertically different positions, wherein the insulating layers 25a and 25b are each slanted and extend in the seal ring 11 in such a way that the insulating layer 25a covers the insulating layer 23, and the insulating layer 25b covers the insulating layer 25a. 
The GMR elements 6 to 9 and a wiring layer 24c are formed on a planar surface of the insulating layer 25b, and a metal layer 26, which is formed in the same level of the wiring layer 24c, is formed in a slanted surface of the insulating layer 25b, which extends in the seal ring 11, in such a way that the lower end thereof is brought into contact with the p-type silicon substrate 21. In addition, a passivation film (or a protective insulating layer) 28 composed of silicon nitride is formed to cover the GMR elements 6-9, wiring layer 24c, and metal layer 26. The wiring layers 24a to 24c are electrically connected with each other by metals filled into via holes.
The passivation film 28 is subjected to patterning such that the lower end thereof is limited within the range of the seal ring 11, so that the exposed region of the p-type silicon substrate 21, which is not covered with the passivation film 28, is used for the scribing line 3.
FIG. 8 is a cross-sectional view showing a second example of a silicon wafer, wherein an IC component 31 is constituted such that a planar insulating layer 32 is formed to cover the GMR elements 6-9 and the wiring layer 24c as well as the upper end of the metal layer 26, and a passivation film 33 is formed to cover the planar insulating layer 32 and the metal layer 26.
FIG. 9 is a cross-sectional view showing a third example of a silicon wafer, wherein a seal ring 41 is subjected to patterning to realize a laminated structure comprising the insulating layer 23, a metal layer 42a that is formed in the same level of the wiring layer 24a, the insulating layer 25a, a metal layer 42b that is formed in the same level of the wiring layer 24b, the insulating layer 25b, and a metal layer 42c that is formed in the same level of the wiring layer 24c. The metal layers 42a, 42b, and 42c are electrically connected with each other by metals filled in via holes. In addition, a planar insulating layer 32 is formed to cover the GMR elements 6-9 and the wiring layer 24c as well as one end of the metal layer 42c; a passivation film 33 is formed to cover the planar insulating layer 32 and the upper portion of the metal layer 42c as well as the end portions of the insulating layers 23, 25a, and 25b, whereby the lower end of the passivation film 33 is limited within the range of the seal ring 41.
As described above, the semiconductor chip having the magnetic sensor is constituted in such a way that the magnetoresistive elements are incorporated into the IC; hence, it can cope with the recent tendencies of electronic devices that are reduced in sizes and dimensions realizing small thickness.
Chip regions corresponding to semiconductor chips having thin-film elements have multilayer structures in which wiring layers including electric circuits and insulating layers are laminated together with respect to the IC components 4 and 31 respectively. Thin-film elements such as magnetic sensors are generally formed using thin films in order to avoid deterioration of properties thereof, wherein passivation layers are formed on multilayer structures to realize planarity.
In the scribing line 3 partitioning chip regions, the surface of the p-type silicon substrate 21 is exposed so as to cause a relatively great height difference; hence, nonuniformity of resist application (i.e., striation) may occur in resist formation regions, which are used to form thin-film elements on the IC components 4 and 31. This causes unwanted deviations of shapes and dimensions of thin-film elements. In addition, there is a possibility that contaminating substances produced by thin-film elements may have adverse effects on the ‘exposed’ silicon-related portions of IC regions.
As disclosed in the aforementioned publication, semiconductor devices such as IC devices and LSI devices have been developed in such a way that thin-film elements such as magnetoresistive elements are formed on ICs via insulating layers, wherein uppermost wiring layers are connected with thin-film elements via openings formed therein.
FIG. 17 is a cross-sectional view showing an example of a semiconductor device accompanied with a thin-film element. That is, a semiconductor device 101 of FIG. 17 is manufactured in such a way that an insulating layer 102 composed of silicon oxide or silicon nitride is formed on the upper portion of an IC formed on a silicon substrate (not shown); and a wiring layer 103 having a prescribed pattern is formed on the insulating layer 102 and is electrically connected with the IC via a via hole (not shown) that is formed in the insulating layer 102.
An insulating layer 104 composed of silicon oxide is formed on the wiring layer 103; and an opening 105 is formed in the insulating layer 104 so as to expose the surface of the wiring layer 103. In addition, a thin-film element 107 is formed in association with the opening 105 of the insulating layer 104 via a wiring layer 106 therefor. Furthermore, an insulating film 108 composed of silicon nitride is formed to encompass peripheral ends of the thin-film element 107.
The insulating film 108 can be formed to entirely cover the upper portion of the thin-film element 107.
Next, a method for forming the opening 105 will be described. As shown in FIG. 18A, vacuum evaporation or sputtering is performed to form the wiring layer 103 having the prescribed pattern on the insulating layer 102; then, the CVD (i.e., Chemical Vapor Deposition) process is performed to form the insulating layer 104, which entirely covers the insulating layer 102 and the wiring layer 103. The spin-coating process is performed to apply a photoresist 109 onto the insulating layer 104. The photoresist 109 is exposed to ultraviolet radiation via a mask (not shown) and is then subjected to development; thus, it is possible to form an opening 109a whose pattern matches the pattern of the mask on the photoresist 109.
Then, plasma etching or reactive ion etching is performed on the insulating layer 104 by using the photoresist 109 as a mask so that the upper surface of the wiring layer 103 is exposed as shown in FIG. 18B, wherein an opening whose pattern matches the pattern of the opening 109a is formed in the insulating layer 104.
As shown in FIG. 18C, the photoresist 109 is removed, and vacuum evaporation or sputtering is performed to sequentially form films using a wiring material 111 and a thin-film element material 112 in association with the wiring layer 103 and the insulating layer 104.
Thereafter, patterning is performed on the wiring material 111 and the thin-film element material 112, thus forming the wiring 106 and the thin-film element 107 shown in FIG. 17. An insulating film is further formed on the insulating layer 104 and the thin-film element 107 and is then subjected to patterning so as to form an insulating film 108 in connection with peripheral ends of the thin-film element 107.
In order to realize desired characteristics of thin-film elements, which are formed on ICs in semiconductor devices, it is preferable to reduce dimensions of thin-film elements and wiring layers therefor in thickness; and it is preferable for wiring layers of thin-film elements to have planar surfaces. Such ‘thin’ wiring layers are formed to lie across openings having cross-sectionally rectangular shapes on ICs. This causes problems in that wiring layers become very thin in proximity to edges of openings and are therefore easy to break compared with normal wiring layers formed in semiconductor devices.
The aforementioned problems may be solved by reducing height differences before the formation of thin-film elements, wherein insulating layers are covered with planar insulating layers. However, it may be difficult to eliminate height differences between ICs and thin-film elements in proximity to edges of openings. That is, in the semiconductor device 101, the opening 105 has sharply rising walls in both sides thereof; hence, the wiring layer 106 may be easy to break in proximity to the opening 105. This reduces the reliability in manufacturing semiconductor devices.
The aforementioned drawback may be solved by forming the upper portion of the wall of the opening roughly in a semi-spherical shape or a tapered shape. This may reduce the possibility regarding breaks of the wiring layer; however, due to the sharpness of the lower portion of the wall of the opening, there remain possibilities in that the wiring layer may be easy to break in proximity to the opening and may be reduced in thickness inside of the opening, which causes reduction of the reliability in manufacturing semiconductor devices.